MOHANAPRIYA, R.; RAJESH, K. A Modified Architecture of Multiplier and Accumulator Using Spurious Power Suppression Technique. International Journal of Students’ Research in Technology & Management, [S. l.], v. 3, n. 2, p. 258–263, 2015. DOI: 10.18510/ijsrtm.2015.324. Disponível em: https://mgesjournals.com/ijsrtm/article/view/ijsrtm.2015.324. Acesso em: 20 may. 2024.