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References
- Venkat Rao, Gaurav Singhal Power Issues In Vlsi Design
- Massoud Pedram DESIGN TECHNOLOGIES FOR LOW POWER VLSI
- www.ee.ncu.edu.tw/~jfli/vlsi21/lecture/ch04.pdf by L Benini and G De Micheli
- http://www.ee.ncu.edu.tw/~jfli/vlsi21/lecture/ch04.pdf by Jin-Fu Li; Advanced Reliable
- Systems (ARES) Lab. D
- epartment of Electrical Engineering, National National Central University Central
- University, Jhongli, Taiwan
- MICRO TRANSDUCTORS ’08 OW POWER VLSI DESIGN 2 by Dr.-Ing. Frank Sill;
- Department of Electrical Engineering, Federal University of Minas Gerais, Av. Antônio
- Carlos 6627, CEP: 31270-010, Belo Horizonte (MG), Brazil [email protected],
- ttp://www.cpdee.ufmg.br/~frank/
- LOW POWER DESIGN: CLOCK GATING by M. Ohashi, Matsushita
- LOW-POWER MULTI-THRESHOLD CMOS CIRCUITS OPTIMIZATION AND CAD
- TOOL DESIGN
- A Thesis Presented to The Faculty of Graduate Studies of The University of Guelph by
- WENXIN WANG In partial fulfillment of requirements for the degree of Master of Science
- May, 2004 ,Wenxin Wang, 2004 Advisors: Professor Shawki Areibi, Mohab Anis
- LEAKAGE POWER REDUCTION IN CMOS VLSI CIRCUITS BY INPUT VECTOR
- CONTROL by Afshin Abdollahi, Farzan Fallah, and Massoud Pedram IEEE
- TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,
- VOL. 12, NO. 2, FEBRUARY 2004
- TRANSISTOR AND CIRCUIT DESIGN OPTIMIZATION FOR LOW-POWER CMOS By
- M.Chang, C.Chang,C.Chao, K.Goto,M.Leong, L.Lu,and C.Diaz Presented By Mozammel
- Haque For the Low-Power High- Sped VLSI ELEC 5705Y W-2009
- CMOS DIGITAL INTEGRATED CIRCUITS by Sung- Mo Kang and Yusuf Lablebici Tata
- McGraw-Hill Education, 2003
- SHORT CIRCUIT POWER REDUCTION BY USING HIGH THRESHOLD TRANSISTORS
- by Arkadiy Morgenshtein Received: 15 October 2011; in revised form: 13 February 2012 /
- Accepted: 21 February 2012 /Published: 1 March 2012 Journal of Low Power Electronics and
- Applications ISSN 2079-9268 www.mdpi.com/journal/jlpea/
References
Venkat Rao, Gaurav Singhal Power Issues In Vlsi Design
Massoud Pedram DESIGN TECHNOLOGIES FOR LOW POWER VLSI
www.ee.ncu.edu.tw/~jfli/vlsi21/lecture/ch04.pdf by L Benini and G De Micheli
http://www.ee.ncu.edu.tw/~jfli/vlsi21/lecture/ch04.pdf by Jin-Fu Li; Advanced Reliable
Systems (ARES) Lab. D
epartment of Electrical Engineering, National National Central University Central
University, Jhongli, Taiwan
MICRO TRANSDUCTORS ’08 OW POWER VLSI DESIGN 2 by Dr.-Ing. Frank Sill;
Department of Electrical Engineering, Federal University of Minas Gerais, Av. Antônio
Carlos 6627, CEP: 31270-010, Belo Horizonte (MG), Brazil [email protected],
ttp://www.cpdee.ufmg.br/~frank/
LOW POWER DESIGN: CLOCK GATING by M. Ohashi, Matsushita
LOW-POWER MULTI-THRESHOLD CMOS CIRCUITS OPTIMIZATION AND CAD
TOOL DESIGN
A Thesis Presented to The Faculty of Graduate Studies of The University of Guelph by
WENXIN WANG In partial fulfillment of requirements for the degree of Master of Science
May, 2004 ,Wenxin Wang, 2004 Advisors: Professor Shawki Areibi, Mohab Anis
LEAKAGE POWER REDUCTION IN CMOS VLSI CIRCUITS BY INPUT VECTOR
CONTROL by Afshin Abdollahi, Farzan Fallah, and Massoud Pedram IEEE
TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,
VOL. 12, NO. 2, FEBRUARY 2004
TRANSISTOR AND CIRCUIT DESIGN OPTIMIZATION FOR LOW-POWER CMOS By
M.Chang, C.Chang,C.Chao, K.Goto,M.Leong, L.Lu,and C.Diaz Presented By Mozammel
Haque For the Low-Power High- Sped VLSI ELEC 5705Y W-2009
CMOS DIGITAL INTEGRATED CIRCUITS by Sung- Mo Kang and Yusuf Lablebici Tata
McGraw-Hill Education, 2003
SHORT CIRCUIT POWER REDUCTION BY USING HIGH THRESHOLD TRANSISTORS
by Arkadiy Morgenshtein Received: 15 October 2011; in revised form: 13 February 2012 /
Accepted: 21 February 2012 /Published: 1 March 2012 Journal of Low Power Electronics and
Applications ISSN 2079-9268 www.mdpi.com/journal/jlpea/