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Submitted
September 27, 2015
Accepted
September 27, 2015
Published
September 27, 2015
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Abstract

In this model a runtime cache data mapping is discussed for 3-D stacked L2 caches to minimize the overall energy of 3-D chip multiprocessors (CMPs). The suggested method considers both temperature distribution and memory traffic of 3-D CMPs. Experimental result shows energy reduction achieving up to 22.88% compared to an existing solution which considers only the temperature distribution.  New tendencies envisage 3D Multi-Processor System-On-Chip (MPSoC) design as a promising solution to keep increasing the performance of the next-generation high performance computing (HPC) systems. However, as the power density of HPC systems increases with the arrival of 3D MPSoCs with energy reduction achieving up to 19.55% by supplying electrical power to the computing equipment and constantly removing the generated heat is rapidly becoming the dominant cost in any HPC facility.

Keywords

MPSoC HPC CMP Interconnect TSV Cache Management.

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Authors retain the copyright without restrictions for their published content in this journal. IJSRTM is a SHERPA ROMEO Journal. 

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This is an open-access article distributed under the terms of  Creative Commons License

 

How to Cite
Kumar, K. S., Anitha, S., & Gayathri, M. (2015). 3D Stacked Cache Data Management for Energy Minimization of 3D Chip Multiprocessor. International Journal of Students’ Research in Technology & Management, 3(2), 264–268. https://doi.org/10.18510/ijsrtm.2015.325
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