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Abstract
As the technology moving towards lower voltage for high stability and accurate performance. We design low voltage current mirror using IGFET, FDSOI, CNTFET.These transistor moving towards low-voltage high-speed performance. Here in this paper, we have design low voltage current mirror for Accurate duplication of current. To obtain accurate duplication of current we verify the performance of low voltage current mirror on FDSOI and CNTFET Transistor having 32nm technology.
The circuit is simulated with 32nm technology for FDSOI and CNFET. They operate at lower power supply than IGFET. The simulation results show the improvement in knee voltage 1.7v and 1.3v for the current mirror.
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References
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- http://nptel.ac.in/courses/106104024/2
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References
Minghong Li, H.L. Kwok ‘’The Application of Current-mode Circuits in the Design of an A/D Converter ‘’ Electrical and Computer Engineering, 1998. IEEE Canadian Conference on, Volume 1, 24-28 May 1998Page(s):41 – 44
http://nptel.ac.in/courses/106104024/2
Kuo-Hsing Cheng, Chi-Che Chen and Chun-Fu Chung ‘’AccurateCurrent Mirror with High Output Impedance’’ Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference, Volume 2, 2-5 Sept. 2001 Page(s):565 – 568
Kuo-Hsing Cheng', Tsung-Shen Chen2, and Ching-Wen Kuo ‘’High accuracy current mirror with low settling time’’ Circuits and Systems, 2003. MWSCAS '03. Proceedings of the 46th IEEE International Midwest Symposium, Volume 1, 27-30 Dec. 2003 Page(s):189 – 192 Vol. 1
Milind Subhash Sawant, Jaime Ramirez-Angulo, Antonio. J. Lopez- Martin and Ramon G. Carvajal ‘’ New compact implementation of a very high performance CMOS current mirror’’ circuits and systems, 2005.48th Midwest Symposium, 7-10 Aug. 2005 pp. 840-842
D. Markovic, C.C.Wang, L.P.Alarcon,T.-T.Liu, J.M.Rabaey, “Ultra low- power design in near threshold region,†Proc. IEEE, Vol. 98, no. 2, pp. 237–252, 2010. DOI: https://doi.org/10.1109/JPROC.2009.2035453
S. Chandra, A. Raghunathan, S. Dey, “Variation-aware voltage level selection,†IEEE Trans.VLSI Syst, Vol. 20, no. 5 pp. 925–936, 2012. DOI: https://doi.org/10.1109/TVLSI.2011.2126050
Jie Deng and H.-S.Philip Wong. A compact spice model for carbon-nanotube field-effect transistors including nonidealities and its application - part i: model of the intrinsic channel region. IEEE Transactions on Electron Devices, 54:3186–3194, 2007. DOI: https://doi.org/10.1109/TED.2007.909030
T. Dang , I. Anghel , and R. leveugle , “ CNTFET Basics and Simulationâ€, IEEE International conference on Design and Test of Integrated Systems in Nanoscale Technology (DTIS), Tunis, Tunisia, pp. 28-33, September, 5-7, 2006. DOI: https://doi.org/10.1109/DTIS.2006.1708731
J. Guo, S. Datta, M. Lundstrom, “Assessment of silicon MOS and carbon nanotube FET performance limits using a general theory of ballistic transistorsâ€, IEDM, pp. 711-715, 2002.
Appenzeller "Carbon Nanotubes for High-Performance ElectronicsProgress and Prospect," Proc. IEEE, Volume 96, Issue 2, pp. 201 - 211, Feb. 2008. DOI: https://doi.org/10.1109/JPROC.2007.911051
COLINGE J P. “Silicon on insulator technology: materials to VLSIâ€. 2nd ed. Norwell, MA: Kluwer: Kluwer Academic Publishers; 1997. DOI: https://doi.org/10.1007/978-1-4757-2611-4
Guegan, G., Gwoziecki, R., Touret, P., Raynaud, C., Deleonibus, S., Pretet, J., Gonnard, O., Gouget, G., "New floating-body effect in partially depleted SOI pMOSFET due to direct-tunneling current in the partial n+ poly gate", Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European, On page(s): 59 – 62. DOI: https://doi.org/10.1109/ESSDERC.2008.4681698
Mercha, A., Rafi, J.M., Simoen, E., Augendre, E., Claeys, C., "Linear kink effect induced by electron valence band tunneling in ultrathin gate oxide
bulk and SOI MOSFETS", Electron Devices, IEEE Transactions on, On page(s): 1675 - 1682 Volume: 50, Issue: 7, July 2003. DOI: https://doi.org/10.1109/TED.2003.814983
Behzad Razavi, Design of CMOS Analog Integrated Ckts, Mc-Graw Hill College, 2001.