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Submitted
September 27, 2015
Accepted
September 27, 2015
Published
September 27, 2015
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Abstract

High speed and low power Multiplier and Accumulator (MAC) unit is at most requirement of today’s VLSI systems and digital signal processing (DSP) applications like FFT, Finite Impulse response filters, convolution etc. In this modified architecture, Radix-4 Modified Booth Encoding (MBE) is used to produce the partial products. In this multiplication and accumulation has been combined using a hybrid type of Carry Save Adder (CSA). So the performance will be improved.
A Carry Look ahead Adder is inserted in the CSA tree to reduce the number of bits in the final adder. In booth multiplication, when two numbers are multiplied some portion of the data may be zero. By neglecting those data, power has been reduced. For this purpose Spurious Power Suppression Technique (SPST) is used to remove useless portion of the data in addition process. In this modified architecture, the overall process is three stages to produce the result. The modified MAC operation is coded with Verilog and simulated using Xilinx 12.1.

Keywords

DSP MAC Radix-4 Modified Booth Encoding CSA CLA SPST Verilog.

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Authors retain the copyright without restrictions for their published content in this journal. IJSRTM is a SHERPA ROMEO Journal. 

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How to Cite
Mohanapriya, R., & Rajesh, K. (2015). A Modified Architecture of Multiplier and Accumulator Using Spurious Power Suppression Technique. International Journal of Students’ Research in Technology & Management, 3(2), 258–263. https://doi.org/10.18510/ijsrtm.2015.324
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